The present invention relates to a mixed-signal-controlled phase-locked loop (PLL) and a method for controlling a phase-locked loop by both analog and digital signals.
The phase-locked loops (PLL) have been widely used in high-speed digital systems, disk storage systems, and communication systems. The main functions of the PLL include the time-pulse shifting modulation, the internal time-pulse frequency multiplication, the carrier wave synchronization, and the timing synchronization. As an example, the frequency synthesizer is designed according to the function of the frequency multiplication of the PLL.
Conventionally, the frequency synthesizer is constructed by the use of an analog PLL. The analog PLL includes a voltage control oscillator (VCO) to generate a periodic signal synchronized to a particular reference signal. The frequency of the periodic signal is controlled by an analog voltage, which is modulated through a feedback loop. Generally, the feedback loop includes a phase frequency detector (PFD) and a loop filter. The PFD is used for generating an xe2x80x9cUPxe2x80x9d or xe2x80x9cDNxe2x80x9d pulse which represents the polarity of the phase difference between the periodic signal and the reference signal. The loop filter including a charge pump circuit and a resistance-capacitance (RC) filter is used for integrating the pulse generated from the PFD to output a control voltage. This control voltage generated from the loop filter is fed back to control the frequency of the periodic signal generated from the VCO. The control of the control voltage over the frequency of the periodic signal is continuous and, therefore, the analog PLL can provide a good frequency resolution.
However, the bandwidth of the analog PLL has to be carefully designed to let the signal generated from the PLL have a proper damping characteristic and a low phase noise. If the gain of the loop is too large, the analog PLL will be unstable and the phase will jitter. If the gain of the loop is too small, the phase-locked loop will not have a capacity for adjusting the phase shifting generated from the voltage and temperature changes. The bandwidth of the analog phase-locked loop usually is one tenth of the frequency of the reference signal. In order to obtain both a fast stability and a sufficient phase-shifting endurance, an independent frequency-locked loop (FLL) and an independent analog PLL are designed to function together with one or two VCO.
The all-digital PLL includes a digital controlled oscillator (DCO) and a digital circuit for detecting the frequency and phase. Because a special algorithm is used to search for the digital control word in the digital controlled oscillator, the digital phase-locked loop can capture the frequency in only 50 time-pulse cycles. Therefore, the speed of the all-digital PLL in capturing frequency is much faster than that of the analog PLL. Although the all-digital PLL is programmable, it still has some problems. Namely, the frequency resolution is not as good as the analog PLL and the all-digital PLL is sometimes not suitable for high-frequency uses.
The analog PLL has a better frequency resolution but the speed for capturing the frequency is slow. The all-digital PLL is programmable and has a high speed for capturing the frequency but the frequency resolution is not good enough to be utilized as a frequency synthesizer. It is therefore attempted by the applicant to deal with the above situation encountered with the prior art.
An objective of the present invention is to provide a mixed-signal-controlled phase-locked loop and a method for controlling the same by both the analog and the digital control signals.
Another objective of the present invention is to provide a mixed-signal-controlled phase-locked loop and a method of controlling the same at a fast frequency acquisition speed.
A further objective of the present invention is to provide a mixed-signal-controlled phase-locked loop with a low phase noise and a high frequency resolution.
According to the first aspect of the present invention, a mixed-signal-controlled phase-locked loop includes a mixed-signal-controlled oscillator circuit for generating an oscillating signal having an oscillating frequency and a phase in response to a digital control signal and an analog control signal, a phase-frequency detector circuit electrically connected to the mixed-signal-controlled oscillator circuit, detecting the phase and the oscillating frequency of the oscillating signal and comparing the phase and the oscillating frequency with those of a reference signal to generate an error signal after the phase and oscillating frequency are detected, and a mixed-control-signal-producing circuit electrically connected to the mixed-signal-controlled oscillator circuit and the phase-frequency detector circuit for receiving the error signal to output the analog control signal and the digital control signal to the mixed-signal-controlled oscillator circuit.
In accordance with the present invention, the mixed-control-signal-producing circuit includes an analog-control-signal-producing circuit for receiving the error signal to output the analog control signal to the mixed-signal-controlled oscillator circuit, and a digital-control-signal-producing circuit for receiving the error signal to output the digital control signal to the mixed-signal-controlled oscillator circuit.
Preferably, the digital control signal is a digital control word and the analog control signal is an offset current. The error signal includes an UP signal and a DN signal which are used to identify three different states between the reference signal and the oscillating signal. These three different states are: (1) (UP, DN)=(0,0): the phases and the frequencies of the reference signal and the oscillating signal are synchronous; (2) (UP, DN)=(1,0): the phase of the reference signal leads that of the oscillating signal, so the oscillating frequency has to be increased to catch up with the reference signal; and (3) (UP, DN)=(0,1): the phase of the reference signal lags behind that of the oscillating signal, so the oscillating frequency has to be decreased to make the reference signal catch up with the oscillating signal.
Preferably, the mixed-signal-controlled phase-locked loop further includes a programmable frequency divider electrically connected to the mixed-signal-controlled oscillator circuit for dividing the oscillating signal, and a delay interpolation circuit electrically connected to the programmable frequency divider and the phase-frequency detector circuit for diminishing phase noises contained in the divided oscillating signal.
Preferably, the mixed-signal-controlled oscillator circuit includes a digital control word circuit electrically connected to the digital-control-signal-producing circuit for receiving the digital control word to control a digital control current source to output a digital control current in proportion to the digital control word, and a current-controlled oscillator electrically connected to the analog-control-signal-producing circuit for receiving the offset current and the digital control current to generate the oscillating signal.
In addition, the current-controlled oscillator is a circuit worked with a current mode of symmetric loads, preferably a 3xc3x973 array oscillator.
According to the present invention, the analog-control-signal-producing circuit includes a charge pump circuit electrically connected to the phase-frequency detector circuit for charging and discharging electricity into a loop filter according to the error signal, a loop filter electrically connected to the charge pump circuit for outputting a voltage signal, and a voltage-to-current converter electrically connected to the loop filter and the mixed-signal-controlled oscillator circuit for converting the voltage signal into the offset current to be inputted into the offset input of the mixed-signal-controlled oscillator circuit.
In accordance with the present invention, the digital-control-signal-producing circuit includes a digital control signal generator electrically connected to the phase-frequency detector circuit for receiving the error signal to generate two specific digital signals, and a digital control word algorithm circuit electrically connected to the digital control signal generator for outputting the digital control word into a digital control word input of the mixed-signal-controlled oscillator circuit in response to the two specific digital signals.
Preferably, the two specific digital signals are a SUB signal and a BYPASS signal. When the SUB signal is received, the digital control word algorithm circuit increases/decreases a step size in the digital control word. When the BYPASS signal is received, the digital control word algorithm circuit is disabled from changing the digital control word.
According to the second aspect of the present invention, a method for controlling a phase-locked loop includes the steps of: (a) generating an oscillating signal having an oscillating frequency and a phase in response to a digital control signal and an analog control signal, (b) detecting the oscillating frequency and the phase of the oscillating signal, (c) comparing the phase and the oscillating frequency with that of a reference signal to generate an error signal, and (d) outputting the analog control signal and a digital control signal in response to the error signal to enable the phase-locked loop to be controlled.
Preferably, the digital control signal is a digital control word and the analog control signal is an offset current.
In accordance with the present invention, after step (a), the method further includes the steps of (a1) dividing the oscillating signal, and (a2) decreasing the phase noises in the divided oscillating signal.
In addition, step (c) further includes (c1) generating a voltage signal by charging and discharging electricity into the loop filter according to the error signal, and (c2) converting the voltage signal into the offset current.
In addition, step (d) further includes (d1) generating two specific digital signals in response to the error signal, and (d2) outputting the digital control word in response to the two specific digital signals.